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[Other resource] firISPdesign

Description: fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现，包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware description of the filter language , including the VHDL language and verilog
Platform: | Size: 112475 | Author: xiong | Hits:

[Embeded-SCM Develop] firfilterverilog

Description: 用VERILOG语言实现的FIR数字滤波器-VERILOG language with the FIR digital filter
Platform: | Size: 243712 | Author: 叶少朋 | Hits:

[VHDL-FPGA-Verilog] verilogFir

Description: 基于Verilog+HDL的FIR数字滤波器设计与仿真 -Verilog+ HDL based on the FIR digital filter design and simulation
Platform: | Size: 167936 | Author: 王楚宏 | Hits:

[Embeded-SCM Develop] a

Description: 个人整理的关于FIR滤波器、加法器、减法器的verilog程序，供大家下载-It’s about some programs about filter，and some others I‘ll be happy if it s better for you~~~
Platform: | Size: 4096 | Author: SkySeraph | Hits:

[VHDL-FPGA-Verilog] verilogFIR

Description: 本源码为Verilog的FIR数字滤波器 测试后性能很不错的-The source of the FIR digital filter for the Verilog test performance is very good
Platform: | Size: 638976 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] ser_fir

Description: 用verilog实现一个8阶的改进串行FIR低通滤波器，输入数据位宽为12比特,经符号扩展后变为13比特。-With verilog order to achieve an improvement of 8 serial FIR low-pass filter, the input data bit width of 12 bits by sign extension into a 13-bit after.
Platform: | Size: 1024 | Author: hgdlsl | Hits:

[VHDL-FPGA-Verilog] FIR_Lowpass

Description: 用Verilog HDL编写的FIR低通滤波器。FIR低通滤波器采用8阶串行方式实现。-Written using Verilog HDL FIR low-pass filter. FIR low-pass filter 8-order serial.
Platform: | Size: 796672 | Author: 李桐 | Hits:

[VHDL-FPGA-Verilog] fir_lowpass

Description: 简易FIR低通滤波器的verilog代码-Simple FIR low-pass filter verilog code
Platform: | Size: 1024 | Author: 谢文斌 | Hits:

[VHDL-FPGA-Verilog] fir_verilog_matlab

Description: 本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.
Platform: | Size: 1352704 | Author: 郭婷 | Hits:

[VHDL-FPGA-Verilog] 20140825

Description: FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
Platform: | Size: 5541888 | Author: lirui | Hits:

[VHDL-FPGA-Verilog] 1

Description: verilog编写的11阶FIR数字滤波器-The 11 order FIR digital filter Verilog prepared!!!!!!!!!!!!!!!!!!!!!
Platform: | Size: 681984 | Author: 网速卡 | Hits:

[Other Embeded program] FIR32

Description: 基于DA算法的FIR带通滤波器设计，应用于FPGA实现，verilog语言描述-DA algorithm based on FIR bandpass filter design, used in FPGA implementation, verilog language to describe
Platform: | Size: 3072 | Author: Awei | Hits:

[source in ebook] Digital-signal-process-of-PFGA

Description: 数字信号处理 包括滤波器IIR FIR CORDIC的FPGA实现 资料中是VHDL语言 相应的配套包verilog程序-Digital signal processing includes a filter IIR FIR CORDIC on FPGA is VHDL language data corresponding supporting package verilog program
Platform: | Size: 10710016 | Author: liyinghui | Hits:

[VHDL-FPGA-Verilog] dac_900

Description: DAC900芯片驱动的Verilog语言描述，亲测可用。另外的是FIR滤波代码和DDS波形发生器的代码。既可单独使用，也可以整合在一起。-DAC900 chips driven Verilog language description, pro-test available. Another is the FIR filter code and DDS waveform generator code. Either used alone or can be integrated.
Platform: | Size: 43008 | Author: 唐宏伟 | Hits:

[VHDL-FPGA-Verilog] FIR_filter

Description: 基于FPGA实现FIR滤波器功能 使用芯片为EP2C8Q208C8N,实现FIR滤波器的设计，使用Verilog语言编程，本例子有工程文件、仿真、波形，经过测试可以使用。-FIR filter function based on FPGA chip to use EP2C8Q208C8N, achieve FIR filter design using Verilog language programming, the present examples are engineering documents, simulation, waveform, tested can be used.
Platform: | Size: 12594176 | Author: 陈怡然 | Hits:

[VHDL-FPGA-Verilog] project_fir_test

Description: 基于verilog的FIR滤波器设计，使用BASYS３作为开发工具-Verilog based FIR filter design, the use of BASYS3 as a development tool
Platform: | Size: 39163904 | Author: kan | Hits:

[VHDL-FPGA-Verilog] dfe_filter

Description: DEF算法的FIR滤波器verilog代码，内有乘法器IP核，可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
Platform: | Size: 2048 | Author: 右下角 | Hits:

[VHDL-FPGA-Verilog] firfilterPfpga

Description: FIR滤波器的仿真，使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件，并产生testbench文件进行仿真。-FIR filter verilog coe testbench
Platform: | Size: 9401344 | Author: dfdqzp | Hits:

[VHDL-FPGA-Verilog] DDS_display

Description: 自己写的FIR八戒低通滤波器，仅供参考(Write your own FIR eight quit low-pass filter, for reference only)
Platform: | Size: 6893568 | Author: laobi_verilog | Hits:
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